In measurement technology FPGAs can be employed, by way of example, which comprise a current load of around 80 μA. On the other hand, applications in measurement technology require, by way of example, precise clocking, i.e. the deviation from the fundamental frequency should not account for more than +/−0.1% or +/−0.2% as the case may be. Such precise clocking with low power consumption cannot be readily provided by commercially available oscillators. It would be possible to generate a very precise clock signal with a PLL (Phase-Locked Loop) circuit integrated into the FPGA, which produces a higher clock frequency, which is based on an external reference clock. However, such PLL-circuits have the disadvantage that their power consumption is too large. As they are, they account for a typical power consumption of around 1 mA, i.e. about 12 times the above mentioned power consumption of the FPGA on its own. This makes the provision of a system clock by means of an integrated PLL-circuit unattractive.